Please use this identifier to cite or link to this item: http://bura.brunel.ac.uk/handle/2438/16009
Title: DC/AC inverter based switched capacitor circuit topology with reduced number of components for low power applications
Other Titles: DC/AC inverter based switched capacitor topology
Authors: Bin Mohd Rozlan, Mohd Helmy Hakimie
Advisors: Darwish, M
Theodoridis, M
Keywords: DC/AC inverter;Switched-capacitor topology;Low total harmonics distortion;Low power domestic application;Reduced component count
Issue Date: 2017
Publisher: Brunel University London
Abstract: This thesis presents a new DC/AC inverter circuit which is based on a switched-capacitor circuit topology with reduced components (power switch and capacitor) count for low power applications. The proposed circuit has distinct features of both voltage boost-up and near sinusoidal (multi-level/staircase) AC output voltage. The main idea is to utilise a simple circuit technique called resonant-based Double Switch Single Capacitor Switched-Capacitor (DSSC SCC) with variable duty cycle Pulse Width Modulation (PWM) control technique in such a way that multi-level voltage can be realised across a capacitor. In order to show the superiority of the applied technique, comparisons with other techniques/circuits configurations are presented. The circuit technique can significantly reduce the number of multiple stages of switched-capacitor circuit cells of the recent switched-capacitor multi-level inverter topology. The proposed inverter (with integrated DSSC SCC technique) can generate a line-frequency with 13-levels near sinusoidal AC output voltage with low total harmonics distortion. The output voltage can be achieved with the least number of components use and only a single DC source is used as an input. The proposed inverter topology is also reviewed against other inverter-based switched-capacitor circuit topology and the well-known multi-level inverter topology. The proposed inverter has shown a tremendous reduction in the total harmonics distortion and circuit component count in comparison with the recent Switched-Capacitor Boost multi-level inverter and the classical Cascaded H-Bridge multi-level inverter. Mathematical analysis shows the design of the proposed inverter and PSPICE simulation result to verify the design is also presented. The practical experiment implementation of the proposed system is presented and proves the correct operation of the proposed inverter topology by showing consistency between simulation results and practical results.
Description: This thesis was submitted for the award of Doctor of Philosophy and was awarded by Brunel University London
URI: http://bura.brunel.ac.uk/handle/2438/16009
Appears in Collections:Electronic and Computer Engineering
Dept of Electronic and Computer Engineering Theses

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